In a semiconductor memory device such as a dynamic random access memory (referred to as "DRAM"), a memory cell array typically contains multiple sub-arrays 10 such as illustrated in FIG. 1. Each of the sub-arrays 10 contains multiple word lines WLi (for i equal to 1 to m), multiple bit lines BLj (for j equal to 1 to n), and multiple memory cells MC at intersections of the word lines WLi and the bit lines BLj. Each of the memory cells MC includes a switching transistor (charge transfer transistor) and a capacitor. The gates of the switching transistors couple to corresponding word lines WL1 to WLm, and current paths through the switching transistors are between corresponding bit lines BL1 to BLn and a voltage VP through the corresponding capacitors. Bit lines BL1 to BLn of the respective sub-arrays 10 come in pairs. For example, two adjacent bit lines BLj and BL(j+1) constitute a pair. Multiple sense amplifiers 12, each coupled to pairs of bit lines, are between the sub-arrays 10 and shared by two adjacent sub-arrays 10.
As well known in the art, bit line loading and word line loading increases with the number of memory cells coupled to a word line and a bit line, respectively. Increasing the bit line loading generally increases bit line capacitance and requires improvements in the sensing capability of an attached sense amplifier. Otherwise, the sense amplifier may have difficulty when attempting to sense and amplify a voltage difference between bit lines within a required sensing time. Generally, the sensing capability must match the bit line loading. Accordingly, the sensing ability of the sense amplifiers limits the maximum number of memory cells that can be coupled to a bit line.
Generally, to simplify addressing of the word lines, the number of memory cells on each bit line of each sub-array 10 is a power M of 2 (2.sup.M). If the loading per memory cell on the respective bit line is halved, two sub-arrays can be combined into a sub-array having bit lines that are twice as long, and the sense amplifiers can still service the larger sub-array. To achieve the same total memory capacity, a memory with the larger sub-arrays requires fewer sub-arrays and fewer sense amplifier regions between the sub-arrays. Similarly, a two-fold improvement in the sense capability of the sense amplifiers allows doubling of the bit line loading, decreasing the number of sub-arrays 10 by half, and reducing the number of sense amplifiers 12 required for a fixed total memory capacity. However, if the sensing capability of the sense amplifiers or the bit line loading is not improved by at least a factor of two, the number of sense amplifier regions cannot be reduced because conventional addressing requires the subarrays to contain 2.sup.M memory cells per bit line. The number of memory cells per bit line cannot be doubled unless sensing capability improves by at least a factor of two. Accordingly, when the sensing capability of the sense amplifiers improves by 1.5 times or the bit line capacitance decreases by 25%, the number of the sub-arrays must be maintained despite the improvement. This means the loss of chip efficiency.